Area Efficient Dual-Fed CMOS Distributed Power Amplifier

A 28-36 GHz Optimized CMOS Distributed Doherty Power Amplifier with A New Wideband Power Divider Structure

Background and Objectives: In this paper, a new design strategy was proposed in order to enhance bandwidth and efficiency of power amplifier. Methods: To realize the introduced design strategy, a power amplifier was designed using TSMC CMOS 0.18um technology for operating in the Ka band, i.e. the frequency range of 26.5-40GHz. To design the power amplifier, first a power divider (PD) with a ver...

Dual Fed Distributed Amplifier with Controlled Termination Adjustment

A new circuit and technique to extend the bandwidth of the Dual Fed Distributed Amplifier (DFDA) while preserving the improvement on efficiency performance in comparison to conventional distributed amplifiers (DAs) is presented. The theoretical analysis is described in detail, and a test vehicle is realized to demonstrate the effectiveness of the proposed method. Output power of ∼ 29 dBm, gain ...

Fully Integrated CMOS Power Amplifier

Area and power efficient trellis computational blocks in 0.13µm CMOS

Improved add-compare-select and branch metric units are presented to reduce the complexity in the implementation of trellis-based decoding architectures. These units use a complementary property of the best rate 1/2 convolutional codes to reduce both area requirements and power consumption in a silicon implementation with no loss in decoding performance. For a 0.13μm CMOS process, synthesized c...

Analysis of Low Power and Area efficient CMOS Comparator Design

In this Paper presents a new dynamic comparator is compared in terms of their voltage, speed and power. A new dynamic comparator which shows lower input offset voltage and high load drivability than the conventional dynamic comparators. This comparator not only achieves low offset but also exhibit high speed and low power in its operation, which can be used for low power high speed ADC applicat...